Yun-Tsung Lai's page
Welcome to Yun-Tsung Lai's page

Personal Information

Name: Yun-Tsung LAI (賴 昀樅)
Affiliation: High Energy Accelerator Research Organization (KEK), Institute of Particle and Nuclear Studies (IPNS), Electronics System (E-sys) group.
Position: Assistant Professor
Address: 305-0801, 1-1 Oho, Tsukuba, Ibaraki, Japan

If you are looking for a Ph.D. position for experimental high-energy physics, and are interested in:

please contact me via email anytime!
You are welcome to join us with the Sokendai (総合研究大学院大学) Ph.D. course.

Research Experience

Belle II experiment      link

  Belle II L1 Trigger (TRG)

  • Charged tracking algorithms, FPGA firmware development/maintenance for the track trigger system (CDCTRG) as one of the major manager of the system.
  • Development/maintenance on CDCTRG Merger board: firmware design, mass production and quality check.
  • Fully user-defined data transmission protocol design for optical link in TRG for Xilinx and Altera FPGA chips.
  • Data readout to central DAQ using Belle2Link protocol. Extension of the protocol to different Xilinx MGT.
  • Global Reconstruction Logic (GRL): Summary of Level-1 trigger. Matching algorithm between CDC track trigger and outer sub-detector’s information. Tracking algorithm for CDC short track.
  • Firmware design for the next generation of universal trigger board (UT4): New data transmission protocols with higher speed using Xilinx UltraScale FPGA's MGT.
  • Software in Belle II software framework (basf2): Manager of entire TRG software package. Development/maintenance of L1 algorithms for simulation, and offline data unpacker and processor.
  • Co-Investigator of 科研費 “ダークマターの正体は何か?- 広大なディスカバリースペースの網羅的研究” 計画研究 B05 “電子陽電子加速器によるダークマター探索”: Trigger performance study and new trigger development for Dark Sector search and low-multiplicity physics processes.

  Belle II Aerogel-Based Ring-Image Cherenkov counter (ARICH)

  • Firmware design and maintenance for ARICH Front-end and Merger electronics boards: Implementation of Belle2Link protocol for data taking. Real-time Single-Event-Upset (SEU) monitoring and treatment in FPGA.
  • Maintenance of the ARICH DAQ system: as the leadership for the operation management of the ARICH DAQ system.
  • Particle identification likelihood performance check for ARICH with Belle II phase2 data and software design.

  Belle II DAQ

  • Maintenance of data readout firmware using the universal Belle2Link protocol: Source codes of Front-End electronics and readout modules.
  • Firmware development of the DAQ upgrade based on new PCI-express-based readout board (PCIe40). Slow control software development in readout server for PCIe40. Commissioning for the upgrade of different Belle II sub-detector systems.
  • High-Level-Trigger system (HLT) with ZeroMQ implementation: An open-source universal messaging library.

Belle experiment      link

  • Baryonic B decays.
  • Development of the charm tagger method, and search for D0 decay to invisible final state.
  • Charmless three-body B decays: Search for the resonant state and localized CP asymmetry in the phase space.

Work Experience

  • Oct 2022 - Present: Assistant Professor @ KEK, IPNS, Tsukuba, Japan.      KEK IPNS

  • Jun 2020 - Sep 2022: Project researcher @ University of Tokyo, Kavli IPMU, Kashiwa, Japan.      Kavli IPMU

  • Jun 2017 - May 2020: Postdoc researcher @ KEK, IPNS, Tsukuba, Japan.     

  • Sep 2016 - May 2017: Postdoc researcher @ National Taiwan University, Department of Physics, Taipei, Taiwan.      NTU NTUHEP


  • Jan 2012 - Sep 2016: Doctor degree @ National Taiwan University, Department of Physics, Taipei, Taiwan.

  • Jul 2008 - Jan 2012: Bachelor degree @ National Taiwan University, Department of Physics, Taipei, Taiwan.


Please refer to: pdf