/batch
/page,,,500,132
/prep7
/title,type-R,XXXfile,BeO-bridge,Qamp/Qsi=XXXqamp/XXXqsiW,Tcool=XXXh2o,no convection
c***********rphi-center-tap 97-March configuration*********
c******* flat cooling plate, narorow stand********
c******* effect of bonding wires included (96.8.24)******
c******* new thermal conductivities, t(glue)=0.05->0.1 mm (96.8.26)
c******* 1 side cooling, PG base board of .5mm **********
c******* fineri three division near the z edge of the hybrid******
c******* divide hybrid into two in height(y)  **********
c******* anisotropic conductivity of PG introduced (96.8.26) ****
c****** airgap between bridge and cooling plate*****
c****** glue3 under the chips ************
c******* extend PG right side to 119mm (tongue 109mm)*****
c****** R model (Mar 22, 1997)*****
disp=0
pchp1=XXXqamp*1.3/3.0  ! power in 1st chip (Watt) per side(6 chips)
pchp2=XXXqamp*0.2/3.0   ! power in 2nd chip (Watt) per side(6 chips)
tpwsi=XXXqsi    ! total power dissipation in Si
th2o=XXXh2o      ! cooling cahnnel water temperature on A side
hcef=0.000008  ! convection film coefifcient : Watt/(mm**2 K)  
tenv=XXXtev           ! temperature of environment
c****silicon, 3 dimentional model*******************************
et,1,solid69
et,2,solid70
c***** material properties******************************
mp,kxx,1,0.130         ! 1. Silicon 
mp,kxx,4,0.0005         ! 4. glue
mp,kxx,5,0.001       ! insulator
mp,kxx,6,0.00025       ! hybrid (effective)
mp,kxx,7,0.280           ! Beryllia (BeO)
mp,kxx,8,0.0000245      ! air
mp,kxx,9,0.0015      ! quarz
mp,kxx,11,0.130         ! VLSI chip1
mp,kxx,12,0.130         ! VLSI chip 2
mp,kxx,15,0.00220      ! effective bonding wires (150/50.96=2.94*0.3/0.4)
mp,kxx,17,1.300         ! PG  conductivity in the plane
mp,kzz,17,1.300         ! PG  conductivity in the plane
mp,kyy,17,0.0250        ! PG  conductivity out of the plane
c******************** geometry ***********************************
tbase=0.35                     ! baseboard thickness
tsilicon=0.300               ! silcion thickness
lsilicon=64.0            ! single wafer
wsilicon=63.6                ! silicon width
tchp=0.35                ! chip height
lchp1=4.0
lchp2=5.5
wchp=7.2
c***************** generation of heat in amplifier
vchp1=6*tchp*lchp1*wchp
qgen1=pchp1/vchp1     ! generated power in unit volume
vchp2=6*tchp*lchp2*wchp
qgen2=pchp2/vchp2     ! generated power in unit volume
c**** generation of heat in silicon bulk
voltsi=100
*if,tpwsi,gt,0,then
c*******ssi=2.*2.*lsilicon*wsilicon        ! 2 for top/bottom
pwsi=tpwsi*1.E-6
r0=voltsi*voltsi/(pwsi*tsilicon)
*else
voltsi=1.0e-5
r0=1.e30
*endif
eg=1.23
kb=8.617e-5
T=263
rm10=r0/((T/273)**2*exp(-eg/(2*kb)*(1/T-1/273)))
T=283
r10=r0/((T/273)**2*exp(-eg/(2*kb)*(1/T-1/273)))
T=293
r20=r0/((T/273)**2*exp(-eg/(2*kb)*(1/T-1/273)))
T=303
r30=r0/((T/273)**2*exp(-eg/(2*kb)*(1/T-1/273)))
T=313
r40=r0/((T/273)**2*exp(-eg/(2*kb)*(1/T-1/273)))
T=323
r50=r0/((T/273)**2*exp(-eg/(2*kb)*(1/T-1/273)))
T=333
r60=r0/((T/273)**2*exp(-eg/(2*kb)*(1/T-1/273)))
T=343
r70=r0/((T/273)**2*exp(-eg/(2*kb)*(1/T-1/273)))
T=353
r80=r0/((T/273)**2*exp(-eg/(2*kb)*(1/T-1/273)))
T=363
r90=r0/((T/273)**2*exp(-eg/(2*kb)*(1/T-1/273)))
T=373
r100=r0/((T/273)**2*exp(-eg/(2*kb)*(1/T-1/273)))
mptemp,,-10,0,10,20,30,40
mptemp,7,50,60,70,80,90,100
mpdata,rsvx,1,,rm10,r0,r10,r20,r30,r40
mpdata,rsvx,1,7,r50,r60,r70,r80,r90,r100
c*****     no T dependence for a while
c******mpdata,rsvx,1,,r0,r0,r0,r0,r0,r0
c*****mpdata,rsvx,1,7,r0,r0,r0,r0,r0,r0
c******************define macro*******************************
*dim,dz,array,30
*set,dz(1),-4.0,-4.0,-1.0,-3.5,-3.5,-1.0,-1.0
*set,dz(8),-1.0,-0.6,-2.4,-3.0,-1.8,-3.04,-7.2
*set,dz(15),-3.04,-7.2,-3.04,-7.2,-3.04,-7.2,-3.04
*set,dz(22),-1.8,-3.0,-2.4,-0.6,-1.0,-1.0,-1.0
*set,dz(29),-3.5,-3.5
*creat,znode,mac
n1=arg1
n2=arg2
*do,i,1,30
ngen,2,1000,n1,n2,,0.,0.,dz(i)
n1=n1+1000
n2=n2+1000
*enddo
*end
c****---------------------------------------------------------------
*create,solid,mac
y1=arg1
y2=y1+1
y4=arg2
y3=y4+1
y5=y1+1000
y6=y2+1000
y7=y3+1000
y8=y4+1000
*if,arg3,le,1,then
e,y1,y2,y3,y4,y5,y6,y7,y8
*else
e,y1,y2,y3,y4,y5,y6,y7,y8
*repeat,arg3,1,1,1,1,1,1,1,1
*endif
*end
c****---------------------------------------------------------------
*create,zsolid,mac
z1=arg1
z2=arg2
z3=arg3
jymax=arg5     ! repeat in height (y direction)
*do,jjj,1,arg4
solid,z1,z2,z3
*if,jymax,gt,1,then
   zz1=z1
   zz2=z2
  *do,kkk,2,jymax
  zz1=zz1+100
  zz2=zz2+100
  solid,zz1,zz2,z3
  *enddo
*endif
z1=z1+1000
z2=z2+1000
*enddo
*end
c******************** geometry *****************************
c********************* node creation ***************************
basehalf=tbase*0.5
yyy=basehalf
xxx=0.0
*do,nn,1,6      
n,nn,xxx,yyy,0.
xxx=xxx+5.
*enddo
n,7,27.5,yyy,0.
n,8,30.0,yyy,0.
n,9,32.0,yyy,0.
n,10,34.0,yyy,0.
n,11,38.0,yyy,0.
n,12,42.0,yyy,0.
n,13,47.0,yyy,0.
n,14,52.0,yyy,0.
n,15,57.0,yyy,0.
n,16,62.0,yyy,0.
n,17,64.0,yyy,0.
n,18,64.1,yyy,0.
n,19,67.0,yyy,0.     ! for bonding wires (17-18)
n,20,67.4,yyy,0.
n,21,69.0,yyy,0.
n,22,71.5,yyy,0.
n,23,73.5,yyy,0.
n,24,75.5,yyy,0.
n,25,76.5,yyy,0.
n,26,79.0,yyy,0.
n,27,82.0,yyy,0.
n,28,86.0,yyy,0.
n,29,91.0,yyy,0.
n,30,96.0,yyy,0.
n,31,100.0,yyy,0.
n,32,105.0,yyy,0.
n,33,110.0,yyy,0.
n,34,115.0,yyy,0.
n,35,121.0,yyy,0.
n,36,128.0,yyy,0.
znode,1,36

tglue1=0.075
yyy=yyy+tglue1
hglue1=yyy
ngen,2,100,1,36,,0.,tglue1,0.
znode,101,136

tsilicon=0.30
yyy=yyy+tsilicon
hsilicon=yyy
ngen,2,100,101,136,,0.,tsilicon,0
znode,201,236

tairgap=0.20
yyy=yyy+tairgap
hairgap=yyy
ngen,2,100,219,230,,0.,tairgap,0.
znode,319,330

tbridge=0.381
yyy=yyy+tbridge
hbridge=yyy
ngen,2,100,319,330,,0.,tbridge,0.
znode,419,430

tglue2=0.075
yyy=yyy+tglue2
hglue2=yyy
ngen,2,100,419,430,,0.,tglue2,0.
znode,519,530

thybrida=0.09      * bottom of hybrid
yyy=yyy+thybrida
hhybrida=yyy
ngen,2,100,519,530,,0.,thybrida,0.
znode,619,630

thybridb=0.09      * top of hybrid
yyy=yyy+thybridb
hhybridb=yyy
ngen,2,100,619,630,,0.,thybridb,0.
znode,719,730

tglue3=0.075
yyy=yyy+tglue3
hglue3=yyy
ngen,2,100,719,727,,0.,tglue3,0.
znode,819,827

tchip=0.35
yyy=yyy+tchip
htchip=yyy
ngen,2,100,822,827,,0.,tchip,0.
znode,922,927

c******* now the creation of elements ***********************8

c********* layer of 1 - 100 ***********
type,2
mat,8     ! air between base and silicon
zsolid,6001,6101,35,2,1
zsolid,8001,8101,11,3,1
zsolid,11001,11101,9,2,1
zsolid,13001,13101,8,3,1
zsolid,16001,16101,7,2,1
zsolid,18001,18101,6,2,1
zsolid,20001,20101,5,2,1
zsolid,22001,22101,8,3,1
zsolid,25001,25101,35,2,1
zsolid,8031,8131,5,2,1
zsolid,10032,10132,4,13,1
zsolid,23030,23130,6,2,1
zsolid,8016,8116,3,17,1    ! air near bonding
zsolid,5021,5121,9,1,3      ! between Si and BeO step
zsolid,27021,27121,9,1,3
mat,4     ! glue between base and silicon
zsolid,8012,8112,4,3,1
zsolid,11010,11110,6,2,1
zsolid,13009,13109,7,3,1
zsolid,16008,16108,8,2,1
zsolid,18007,18107,9,2,1
zsolid,20006,20106,10,2,1
zsolid,22009,22109,7,3,1
zsolid,8019,8119,11,17,1
zsolid,8030,8130,1,15,1    
zsolid,10031,10131,1,13,1
zsolid,3021,3121,9,2,1         ! glue of BeO steps
zsolid,28021,28121,9,2,1       ! glue of BeO steps
c********* layer of 100 - 200 ***********
type,1                 
mat,1
zsolid,6101,6201,16,21,1   ! silicon wafer no.1
zsolid,6118,6218,18,21,1   ! silicon wafer no.2
type,2
mat,7      ! BeO steps
zsolid,3121,3221,9,2,2
zsolid,28121,28221,9,2,2
c********* layer of 200 - 300 ***********
mat,8    ! air between Si and BeO bridge
zsolid,6221,6321,9,21,1
c********* layer of 300 - 400 ***********
mat,7     ! BeO bridge
zsolid,3321,3421,9,27,1
c********* layer of 400 - 500 ***********
mat,4     ! glue between BeO bridge and hybrid
zsolid,5421,5521,9,23,1
c********* layer of 500 - 600 - 700 ***********
mat,9      ! quartz fan-in
zsolid,5521,5621,1,23,3
mat,6       ! hybrid
zsolid,5522,5622,8,23,2
c********* layer of 700 - 800 - 900 ***********
c****** macro for chip setting
*create,zchip,mac
zc1=arg1
zc2=zc1+100
zc3=zc1+3
zc4=zc1+103
zc5=zc1+200
zc6=zc1+203
mat,4      ! glue under chips
zsolid,zc1,zc2,2,arg2,1
zsolid,zc3,zc4,2,arg2,1
mat,11     ! CAFE chip
zsolid,zc2,zc5,2,arg2,1
mat,12     ! ABC chip
zsolid,zc4,zc6,2,arg2,1
*end
c*********now create chips and glue
zchip,9722,3
zchip,13722,1
zchip,15722,1
zchip,17722,1
zchip,19722,1
zchip,21722,3

mat,15             ! bonding wires
zsolid,6219,6319,1,21,3
zsolid,6519,6619,2,21,3

c****** copy to bottom side by symmetry*************************
nsel,all
nsym,y,50000,all
ensys,50000,,50000,all

c********** PG baseboard *************************
type,2
mat,8       ! air
zsolid,56001,6001,15,2,1
zsolid,58001,8001,11,2,1
zsolid,61001,11001,9,2,1
zsolid,63001,13001,8,3,1
zsolid,66001,16001,7,2,1
zsolid,68001,18001,6,2,1
zsolid,70001,20001,5,2,1
zsolid,72001,22001,8,3,1
zsolid,75001,25001,15,2,1
zsolid,56031,6031,5,5,1
zsolid,60032,10032,4,13,1
zsolid,73030,23030,6,4,1

mat,17     ! PG base board
zsolid,61010,11010,5,11,1
zsolid,63009,13009,1,9,1
zsolid,66008,16008,1,6,1
zsolid,68007,18007,1,4,1
zsolid,70006,20006,1,2,1
zsolid,60022,10022,10,13,1

mat,7     ! BeO base board
zsolid,58012,8012,3,3,1
zsolid,72009,22009,6,3,1
zsolid,58015,8015,1,17,1
zsolid,50016,16,6,30,1
zsolid,50022,22,9,10,1
zsolid,73022,23022,8,7,1

c****** element creation of cooling plate ***********
mat,4
zsolid,50116,50016,15,2,1
mat,7        * BeO for cooling plate, just one layer
zsolid,50216,50116,15,2,1
fini
c***** end of PREP7 set up *******************

/solusion
c******************** boundary conditions ***************
c*** forced cooling at the side edge of cooling plate ***********
esel,s,mat,,7
nele             * nodes of selected elements
nsel,r,node,,50216,50231
nsel,a,node,,51216,51231
nsel,a,node,,52216,52231
d,all,temp,th2o        * constrain at th20 degree C
nsel,all
esel,all
c*** heat generation in electronics (mat=11)************
esel,s,mat,,11
bfe,all,hgen,1,qgen1,qgen1,qgen1,qgen1
bfe,all,hgen,5,qgen1,qgen1,qgen1,qgen1
esel,s,mat,,12
bfe,all,hgen,1,qgen2,qgen2,qgen2,qgen2
bfe,all,hgen,5,qgen2,qgen2,qgen2,qgen2
esel,all
nsel,all
c****** heat genartion if silicon bulk by appling voltage to Si
esel,s,mat,,1
nele
nsel,r,loc,y,hglue1,,,1        * select nodes of y=0.
d,all,volt,0.
esel,s,mat,,1
nele
nsel,r,loc,y,hsilicon,,,1       * select nodes of y=tsi
d,all,volt,voltsi
nsel,all
esel,all
c***********************************************************
solve
finish
c***********************************************************
/post1
/show,zplot,ps,,4
/view,1,1,1,1
/edge,1,1
plnsol,temp       ! plot birds eye view
c****/contour,1,10,0,1,9
/view,1,0,1,0
/edge,1,1
plnsol,temp       ! plot top view
esel,s,mat,,1
nele
nsel,r,loc,y,0.,hsilicon
plnsol,temp       ! plot silicon only
nsel,all
esel,s,mat,,17
nele
yyy=-basehalf
nsel,r,loc,y,yyy,basehalf
plnsol,temp       ! plot baseboard only
nsel,all
esel,s,mat,,7
nele
nsel,r,loc,y,hairgap,hbridge
plnsol,temp       ! plot BeO bridge only
esel,all
nsel,all
/view,1,-1,0,0
/edge,1,0
/ratio,1,1,20
nsel,s,loc,x,71.0,75.0
enode,1
esel,u,mat,,8
nele
plnsol,temp      ! plot the cross section at amp
esel,all
nsel,all
/ratio,1,1,1
/view,1,0,0,1
/grid,1
/yrange,0,10
/xrange,0,128
/output,zXXXfileXXXout,out
*dim,aa,array,5
*set,aa(1),7201,12201,15201,19201,24201
*do,i,1,5
n1=aa(i)
n2=n1+32
lpath,n1,n2
pdef,t,temp
prpath,t
plpath,t
/noerase
*enddo
fini
/exit,all